Data latches of conventional design are commonly fabricated from a relatively large number of devices. Examples of such conventional data latches are illustrated in FIGS. 1 and 2 of the drawings. The conventional latch of FIG. 1 comprises the interconnection of inverter, NAND and OR gates. Such an arrangement is typically implemented by fifteen transistors and six diodes. The conventional latch of FIG. 2 comprises the interconnection of inverter, AND, and NOR gates. Such an arrangement is typically implemented by sixteen transistors and six diodes.
As will be apparent, data latches which are fabricated from a relatively large number of devices are frequently characterized by large size, slow speed, high power consumption and high cost. What is more, such data latches are often associated with relatively complex write and read circuitry. Therefore, the conventional latches of FIGS. 1 and 2 are particularly unsuitable in large data arrays, whenever size, speed, power consumption and cost are important considerations.